1. Field of the Invention
The present invention relates generally to a semiconductor memory device incorporating a block write function and, more particularly, to a semiconductor memory device for use as an image memory.
2. Related Background Art
Generally, DRAM is often employed as a random-access module (hereinafter abbreviated to RAM module) of an image memory. The RAM module is available as a frame buffer for storing display-oriented data, and a high-speed data rewrite function is therefore required of this RAM module. One of functions which meet this demand may be a block write mode.
A known memory adopting the block write mode is disclosed in U.S. Pat. No. 4,807,189. The arrangement according to this patent is such that when the block write mode is designated by a signal level pattern given to a plurality of specific pins, a plurality of bit lines are simultaneously activated; and the write data are imparted from a data line connected in common to these bit lines.
According to this construction, however, the data line common to the plurality of bit lines is single, and hence it is impossible to freely select whether or not the data are written per column. For this reason, a specified pattern cannot be written.
An improvement in view of such consideration is a device including data lines corresponding to the respective columns. More specifically, a plurality of data lines are provided corresponding to the bit lines of the plurality of unitized columns, and the bit lines are made conductive to the plurality of data lines per unit column.
For instance, a 4-column block write mode is often-used as a typical block write. In this mode, the data are simultaneously written to the four columns irrespective of values of low-order 2 bits A1 A0 of column addresses A8 A7 . . . A1 A0 of the RAM module. Note that selective masking (no data is written) can be performed per I/O bit or column in the block write mode.
FIG. 6 illustrates a semiconductor memory device capable of the above-mentioned 4-column block write. It is assumed that the RAM module of the illustrated semiconductor memory device has 512 columns Ci (i=0, . . . 511). A DQ buffer 40 for linking the RAM module to the peripheral circuits is capable of transferring the data from the RAM module to an output buffer 50 disposed in the peripheral portion while amplifying the data as well as writing the data from a write buffer 20 disposed in the peripheral portion to the RAM module while amplifying the data. The write data is given from the write buffer 20 through a write data line 25 to the DQ buffer. The DQ buffer 40 drives data lines DQ0, DQ1, DQ2 and DQ3. The data lines are generally complementary lines and are arranged in a 2-line set in many cases. Referring to FIG. 6, for simplicity, the data lines are illustrated in the form of a single line. Referring again to FIG. 6, four sets of data lines DQi (i=0, . . . 3) are connected to the DQ buffer 40. Masking must be executable independently with respect to four columns during the block write mode.
When the column addresses A8 A7 . . . A1 A0 are transferred to a column address buffer 30, the column address buffer 30 generates inverted signals Ai of the respective bits Ai (i=0, . . . 8) of the column addresses. High-order 7-bit signals Aj (j=2, . . . 8) of the column addresses and inverted signals Ajthereof are transmitted to a column decoder module CD. Transmitted to the DQ buffer 40 are remaining low-order 2-bit signals Aj (j=0, 1) and inverted signals Ajthereof. The column decoder module is constructed of 128 pieces of column decoders CDi (i=0, . . . 127). Each of the column decoders CDi consists of, as illustrated in FIG. 7, e.g., a NAND circuit and inverter circuits. On the basis of seven signals Xi (i=2, . . . 8), the column decoder CDi generates a signal for selecting a single column selection line CSLi. Each of the signals Xi (i=2, . . . 8) represents a bit value Ai of the column address or its inverted value Ai.
When the column decoder module CD selects one column selection line, e.g., CSL0 among 128 column selection lines CSL0, . . . CSL127 in that manner, an electric potential of the column selection line CSL0 is high, thereby turning ON transfer gate transistors T0, T1, T2, T3. If columns C0, C1, C2, C3 are not masked, the write data transferred from the DQ buffer 40 through the data lines DQ0, DQ1, DQ2, DQ3 are written respectively to memory cells of the columns C0, C1, C2, C3 of the RAM module. Incidentally, if there exists a column to be masked, and when this column to be masked is, e.g., C1, the write data is not transferred from the DQ buffer 40 to the data line DQ1, and it follows that no data is written in the memory cells of the column C1.
Next, an explanation of the operation during a typical 1-bit read/write mode is given. In the case of the 1-bit read/write, as a matter of course, all the bits are given to the column addresses. However, the column selection lines are, as described above, arranged corresponding to the block write. Therefore decoding is performed only with the column addresses A8 A7 . . . A2 exclusive of the low-order 2 bits. For this reason, in the case of a read mode, if the column line selecting lines CSLj (j=0, . . . 127) are selected, the data of four columns C4j, C4j+1, C4j+2, C4j+3 corresponding thereto are read respectively to four sets of data lines DQ0, DQ1, DQ2, DQ3. Then, the DQ buffer 40 effects decoding with respect to the remaining low-order 2-bit column addresses. Only the data for one column are read to a read data line 45.
Furthermore, in the case of a write mode, the data from a write data line 25 are supplied to the DQ buffer 40, wherein low-order 2-bit decoding is carried out. The write data are transferred to only one set of data lines among four sets of data lines DQ0, DQ1, DQ2, DQ3. The data are further written to the memory cell corresponding to the column selection line selected based on the column addresses excluding the low-order 2 bits. Eventually, the memory data are read with respect to sets of data lines corresponding to nonselected remaining 3 columns because of the column selection lines being employed in common.
In the conventional semiconductor memory device, the originally required data is only 1 bit in the case of the 1-bit read/write, and yet the single column selection line is arranged corresponding to the four columns. Hence, the excessive data for three columns are read to the data lines. Similarly, in an 8-column block write, the excessive data for an extra seven columns are read.
The data lines are, as stated earlier, typically arranged in pairs of two lines each. During a period for which no data is supplied, the data lines assume the same electric potential. When data are supplied, one data line is charged or discharged, resulting in a difference in the electric potential therebetween. Then, after reading or writing comes to an end, the data lines are precharged and equalized to the initial electric potential. Therefore, when the electric potentials of the data lines CD0, CD1, CD2, CD3 change, the electric power is invariably consumed. A good deal of electric power consumption needed to the disadvantage of miniaturizing the semiconductor integrated element, and is also an obstacle to an increase in speed.